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| 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74ALVCH16823 18-Bit Bus-Interface Flip-Flop with 3-State Outputs Product Features * PI74ALVCH16823 is designed for low voltage operation * VCC = 2.3V to 3.6V * Hysteresis on all inputs * Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25C * Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25C * Bus Hold retains last active bus state during 3-STATE, eliminating the need for external pullup resistors * Industrial operation at 40C to +85C * Packages available: 56-pin 240 mil wide plastic TSSOP (A) 56-pin 300 mil wide plastic SSOP (V) Product Description Pericom Semiconductors PI74ALVCH series of logic circuits are produced in the Companys advanced 0.5 micron CMOS technology, achieving industry leading speed. The 18-bit PI74ALVCH16823 bus-interface flip-flop is designed for 2.3V to 3.6V VCC operation. It features 3-state outputs designed specifically for driving highly capacitive or relatively lowimpedance loads. This device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. The PI74ALVCH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the Clock Enable (CLKEN) input LOW, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN HIGH disables the clock buffer, thus latching the outputs. Taking the Clear (CLR) input LOW causes the Q outputs to go LOW independently of the clock. A buffered Output Enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The Output Enable (OE) input does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Logic Block Diagram 1 PS8103 04/03/97 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74ALVCH16823 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS Product Pin Description Pin Name OE CLR CLKEN CLK Dx Qx GND VCC Description Output Enable Input (Active LOW) Clear Input (Active LOW) Clock Enable Input (Active LOW) Clock Input (Active HIGH) Data Inputs 3-State Outputs Ground Power Truth Table(1) OE L L L L L H Note: 1. H = L= X= Z= = CLR L H H H H X Inputs CLKEN X L L L H X CLK X L X X D X H L X X X Output Q L H L Q0 Q0 Z Product Pin Configuration High Signal Level Low Signal Level Irrelevant High Impedance LOW-to-HIGH Transition 1CLR 1OE 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 1Q6 GND 1Q7 1Q8 1Q9 2Q1 2Q2 2Q3 GND 2Q4 2Q5 2Q6 VCC 2Q7 2Q8 GND 2Q9 2OE 2CLR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56-Pin V56 A56 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1CLK 1CLKEN 1D1 GND 1D2 1D3 VCC 1D4 1D5 1D6 GND 1D7 1D8 1D9 2D1 2D2 2D3 GND 2D4 2D5 2D6 VCC 2D7 2D8 GND 2D9 2CLKEN 2CLK 2 PS8103 04/03/97 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74ALVCH16823 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ............................................................ 65C to +150C Ambient Temperature with Power Applied .......................... 40C to +85C Input Voltage Range, VIN .................................................... 0.5V to VCC +0.5V Output Voltage Range, VOUT ............................................. 0.5V to VCC +0.5V DC Input Voltage ................................................................... 0.5V to +5.0V DC Output Current .............................................................................. 100 mA Power Dissipation ................................................................................... 1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics (Over the Operating Range, TA = -40C to +85C, VCC = 3.3V 10%) Parame te rs VCC VIH(3) VIL(3) VIN(3) VOUT(3) D e s cription Supply Voltage Input HIGH Voltage VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V 0 0 IOH = - 100mA, VCC = Min. to Max. O utput HIGH Voltage VIH = 1.7V, IOH = - 6mA, VCC = 2.3V VIH = 1.7V, IOH = - 12mA, VCC = 2.3V VIH = 2.0V, IOH = - 12mA, VCC = 2.7V VIH = 2.0V, IOH = - 12mA, VCC = 3.0V VIH = 2.0V, IOH = - 24mA, VCC = 3.0V IOL = 100mA, VIL = Min. to Max. VOL O utput LO W Voltage VIL = 0.7V, IOL = 6mA, VCC = 2.3V VIL = 0.7V, IOL = 12mA, VCC = 2.3V VIL = 0.8V, IOL = 12mA, VCC = 2.7V VIL = 0.8V, IOL = 24mA, VCC = 3.0V O utput HIGH Current VCC = 2.3V VCC = 2.7V VCC = 3.0V VCC = 2.3V VCC = 2.7V VCC = 3.0V VCC - 0.2 2.0 1.7 2.2 2.4 2.0 0.2 0.4 0.7 0.4 0.55 - 12 - 12 - 24 12 12 24 mA V Te s t Conditions (1) M in. 2.3 1.7 2.0 0.7 0.8 VCC VCC Typ.(2) M ax. 3.6 Units Input LO W Voltage Input Voltage O utput Voltage VOH IOH(3) IOL(3) O utput LO W Current 3 PS8103 04/03/97 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74ALVCH16823 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS DC Electrical Characteristics-Continued (Over the Operating Range, TA = 40C to +85C, VCC = 3.3V 10%) Parame te rs De s cription IIN Input Current Te s t Conditions (1) VIN = VCC or GND, VCC = 3.6V VIN = 0.7V, VCC = 2.3V IIN (HOLD) Input Hold Current VIN = 1.7V, VCC = 2.3V VIN = 0.8V, VCC = 3.0V VIN = 2.0V, VCC = 3.0V VIN = 0 to 3.6V, VCC = 3.6V IOZ ICC DICC Output Current (3- STATE Outputs) Supply Current Supply Current per Input @ TTL HIGH Control Inputs Data Inputs Outputs VOUT = VCC or GND, VCC = 3.6V VCC = 3.6V, IOUT = 0mA, VIN = GND or VCC VCC = 3.0V to 3.6V One Input at VCC - 0.6V Other Inputs at VCC or GND VIN = VCC or GND, VCC = 3.3V VO = VCC or GND, VCC = 3.3V 4.5 6.5 7 pF 45 - 45 75 - 75 500 10 40 750 mA M in. Typ.(2) M ax. 5 Units CI CO Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient and maximum loading. 3. Unused Control Inputs must be held HIGH or LOW to prevent them from floating. Switching Characteristics over Operating Range(1) Parame te rs fMAX tPD tEN tDIS CLK CLR OE OE Q CL = 50pf RL = 500W VCC = 2.7V VCC = 2.5V 0.2V From To Conditions (INPUT) (OUTPUT) M in.(2) M ax. M in.(2) M ax. 150 1.0 1.4 1.0 1.8 6.4 6.0 6.5 5.6 150 5.2 5.2 5.7 4.7 VCC = 3.3V 0.3V M in.(2) 150 1.0 1.2 1.0 1.3 4.5 4.6 4.8 4.5 ns M ax.(2) Units Notes: 1. See test circuit and wave forms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 4 PS8103 04/03/97 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74ALVCH16823 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS Timing Requirements over Operating Range Parame te rs fCLOCK tW De s cription Clock Frequency Pulse Duration CLR LOW CLK HIGH or LOW CLR LOW tSU Setup Time Data LOW Data HIGH CLKEN LOW Data LOW tH Hold Time Data HIGH CLKEN LOW De s cription Dt/Dv(3) Input Transition Rise or Fall 0 10 0 10 0 10 ns/V CL = 50pF RL = 500W Conditions VCC = 2.5V 0.2V M in. 0 3.3 3.3 0.7 1.4 1.1 1.8 0.4 0.7 0.2 M ax. 150 VCC = 2.7V M in. 0 3.3 3.3 0.7 1.6 1.1 1.9 0.5 0.1 0.3 M ax. 150 VCC = 3.3V 0.3V M in. 0 3.3 3.3 0.8 1.3 1.0 1.5 0.5 0.8 0.4 ns M ax. 150 Units MHz Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. Operating Characteristics, TA = 25C Parame te r CPD Power Dissipation Capacitance Outputs Enabled Outputs Disabled Te s t Conditions CL = 50pF, f = 10 MHz VCC = 2.5V 0.2V VCC = 3.3V 0.3V Typical 27 16 30 18 Units pF Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com 5 PS8103 04/03/97 |
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